This invention relates to semiconductor devices for information storage. In particular, the invention relates to three-dimensional arrays of vertical thyristors in dynamic random access memories (DRAMs) and methods for fabrication of such memories.
Various DRAM semiconductor cell structures have been proposed using thyristors. The assignee herein describes several thyristor semiconductor structures for DRAMs, and the processes for manufacturing them in various commonly assigned co-pending patent applications. See, e.g., U.S. Patent Application 62/530,785, filed Jul. 10, 2017, and entitled “Vertical Thyristor Dynamic Random Access Memory Cell and Methods of Fabrication,” incorporated by reference herein.
The one-transistor/one-capacitor (1T1C) cell has been essentially the only memory cell used in DRAM devices for the last 30 years. Bit density has quadrupled approximately every 3 years by lithographical scaling and ever increasing process complexity. Maintaining the capacitance value and low transistor leakage have become a major problem for further reductions in cell area.
Recently alternative DRAM cells have been proposed to overcome the scaling challenges of conventional 1T1C DRAM technology. These include floating body DRAM (FBDRAM), a single MOSFET built on either a silicon-on-insulator (Okhonin, Int. SOI Conf., 2001) or in triple-well with a buried n-implant (Ranica, VLSI Technology, 2004). These technologies have yet to solve data retention issues, particularly in small geometry cells.
Various cell designs have been proposed based on the negative differential resistance (NDR) behavior of a PNPN thyristor. An active or passive gate is often used in these designs to optimize trade-offs among switching speed, retention leakage, or operation voltage. The thin capacitively-coupled thyristor (TCCT), as disclosed by U.S. Pat. No. 6,462,359, is a lateral PNPN thyristor constructed on a SOI substrate and has a coupling gate for increased switching speed. Due to its lateral 2D design and the need of a gate, the cell size is larger than the 1T1C cell which is about 6˜8F2.
Recently, Liang in U.S. Pat. No. 9,013,918 disclosed a PNPN thyristor cell that is constructed on top of silicon substrate and operated in forward and reverse breakdown region for writing data into the cell. The use of epitaxial or CVD semiconductor layers at the backend of the standard CMOS process, add-on thermal cycles and etch steps can degrade performance and yield of devices already formed on, or in, the substrate. In addition, PNPN devices operated in the breakdown regime pose challenges in process control and power consumption.
The assignee of this application previously disclosed thyristor memory cells built in a bulk semiconductor substrate used as reference for cell physics and operations. It is advantageous, however, to be able to stack the thyristor cells for multiple layers of memory arrays. This application discloses new 3D stacked thyristor cells, arrays, and sample manufacturing process flows.
This application describes improvements over the technology described in that application.